1. Field of the Invention
The invention relates to a memory cell, and more particularly to a method for forming a vertical memory cell with a buried strap aligned with a trench top oxide layer.
2. Description of the Related Art
Memory devices, such as dynamic random access memory (DRAM), for non-volatile storage of information, are currently in widespread use, in a myriad of applications.
A conventional DRAM consists of a transistor and a capacitor, with electrical charges moving in or out of the capacitor during reading or writing. The capacitor normally used is a deep trench capacitor to reduce the size of the memory device. The capacitor is disposed in the deep trench bottom, the transistor is disposed at the deep trench top, and a thin dielectric layer, such as trenchtop oxide (TTO) layer, acting as an electrical insulating layer is disposed between the capacitor and the transistor.
FIG. 1 is across-section of a conventional vertical DRAM. The vertical DRAM comprises a semiconductor 100 with a deep trench, in which the deep trench is defined by a mask layer consisting of a pad oxide layer 102 and a nitride layer 103. A capacitor 105 is disposed in the deep trench bottom 105, an oxide layer 104 is formed between the capacitor 105 and the trench, a doped poly layer 107 is formed on the oxide layer 104, and a thin nitride layer 106 is formed between the doped poly layer 107 and the oxide layer 104. A trench top oxide (TTO) layer 108 is formed on the elements to insulate the capacitor 105 and a vertical transistor formed thereon. The doped poly layer 107 is annealed to form an ion diffused area 109 acting as a buried strap and a drain, and disposed in the semiconductor substrate 100 beside the TTO layer 108. After a gate oxide layer 110 and a doped poly layer 112 acting as agate are formed, the DRAM with a vertical channel is complete.
As the ion diffused area 109 covers the semiconductor substrate 100 outside the TTO layer 108 and the doped poly layer 112, when the ion diffused area is increased, ion concentration is lowered, thereby increasing the resistance. As a result, writing and reading currents of the capacitor 105 are affected.